Analyzing Effects of Trace Cache Configurations on the Prediction of Indirect Branches

This paper discusses the effects of using a trace cache on the indirect branch prediction in ILP processors. The main contribution of the paper is an exploration of the fact that the trace cache captures context information about the recent control flow of the program, which can improve the accuracy of predictors that do not themselves explicitly use such information. We analyze and experiment with various trace cache configurations and strategies to measure their effects on indirect branch prediction accuracy. We show that updating indirect branch target addresses in the trace cache improves indirect branch prediction accuracy. Then, we incrementally vary the trace cache configuration such as applying trace packing, adding 2-bit update counters per trace cache line, varying trace cache set associativity, cache size and cache line size in order to observe the impact of each configuration on the indirect branch prediction. We simulate a wide variety of designs using benchmarks with higher than average numbers of indirect branches. Our experimental results show that the harmnonic mean indirect branch prediction accuracy for a processor model with a trace cache that updates indirect branch target addresses is 42.04%, compared to 28.82% for a model with a trace cache that does not update indirect branch target addresses, and 10.85% for a model with a branch target buffer on our benchmarks. Our results have implications for any hardware predictor which stores entries corresponding to (possibly replicated) instructions in the trace cache rather than original instructions in main memory.